Minutes from the ATLAS-UK
Level-1 Calorimeter Trigger Meeting
Friday, 13 October, 2000. Birmingham
Present: QMW: E. Eisenhandler (Ch.), D. Mills, E. Moyes. RAL: I.Brawn, N. Gee, T.
Gillman, R. Hatley, V.Perera. Bham: G. Anagnostou, P. Bright-Thomas (Minutes), J.
Garvey, R. Staley, W. Stokes, S. Talbott, P. Watkins, A. Watson.
Minutes by PB-T. These minutes are also
available as ascii
text. This html version generated by BMB.
Tests have been made with a
"new" National Semiconductors LVDS receiver part,with a nominal operating
frequency range of 40-66 Hz (fed by an "old" transmitter, clocked by the TTC
system). From overnight tests of 4 channels with either 15m of AMP cable or 20 m of
Datwyler cable, or 8 channels over 12m of Datwyler cable (limited by available cables) no
errors were observed.
This equates to a BER of better than 5x10-14, in excess of the already adequate <10-12 obtained with the old LVDS receiver part
(although no actual errors were observed, "sanity checks" were made to show that
error trapping was active). Further tests will be made with the system
"stressed", i.e. with attenuated signal and increased system activity.
The new part has the advantages of not requiring a
high stability Tx clock, being more tolerant of supply noise, and being compatible with
relaxed cable equalisation (the latter means that a given R-L combination on the
transmitting module will be compatible with a wider range of cable lengths than with the
old part). The fast Tx equivalent is not yet available in die
form, although packaged parts have been ordered for testing. There is also a "new
slow" Rx part (nominal range 16-40 MHz) and that is also required for testing.
However, it seems that the combination "old slow Tx + new fast Rx" is a
Norman asked if the cable length could now be fixed
after the PPM is designed (fixing RL values), to which the answer was yes. Viraj commented
that if a chip scale tested package is available then bare dies may not be marketed.
Generic Test Module: Viraj
The board layout was completed on 11th October and a
manufacturer is being sought to get a 10-day turnaround on the board fabrication. Firmware
for testing of Serialiser and CP chip is in development, with the module expected to be
available in November.
CP "chip": Viraj
The diagnostic and monitoring block has now been
designed, meaning that all functional blocks are now complete, but require integration.
Test vectors have been made available (ATW) to verify the algorithm block. A device has
not yet been targeted, but it remains possible that the design might fit an XCV1000E, if
not an XCV16000E will be required (same footprint). Test vectors in the format of data
from the Serialiser (4-bit nibbles at 160 Mbps) will be required within 3-4 weeks.
The design is complete meeting spec v1.2. Choice of
package (PQ240 vs FG256) is still to be made, although the former is not really a viable
choice. The Serialiser will first be implemented in an FG680 package on the Generic Test
Module. Exact pin-out allocations for any package have not been made, but there is quite a
lot of freedom to fit the requirements of the CPM.
Generic Test Module tests for Serialiser/CP
The receiver functionality is complete and the pin-out
is fixed, although the timing is not yet verified. The Serialiser test set-up will be
completed within the next month. In discussion, the need for an overall approach to test
vectors for the entire system, perhaps produced by a special working group, was
The main change to the specification since the PDR in
June has been that the FPGA configuration EEPROMS will be replaced by Flash memories.
These are easier to implement, do not require a JTAG interface, are cheaper, and are
higher capacity (hence fewer parts on the CPM). Each FPGA will have only two memory banks
available, since any 3rd configuration required for the CPM can be down-loaded directly
through VME anyway. The flash memories take something like 20 seconds to erase, 8s to
write and 200 ms to down-load to an FPGA. The configuration memories will be down-loaded
in parallel from VME via a buffer of at least 1 kbyte for software efficiency. The plan is
now to review the schematics in November and do the board layout in December.
CP Chip labelling and organisation: Paul
James requires labels and layout for pins of the CP chip, and
the CPM requires a coherent way of naming a large number of real-time signal paths between
20 Serialisers and 8 CP chips on each module. The Serialiser pin-labelling scheme was
re-iterated, which treats the two halves of the Serialiser separately (denoted as X and Y
in the spec). Changes were requested to this labelling so that the 5 160 Mbps lines for
each Serialiser-half could be labelled as a single 5-line bus. The layout of inputs to the
CP chip was shown, with suggestions for labelling input pins by Serialiser from which
their signals come. A labelling format for trigger tower signals was also proposed.
Finally, an approximate pin grouping and position for the CP chip was suggested, taking
account of the layout of the CPM. The use of a similar scheme for the JEM will be
discussed at Heidelberg.
Four ROD modules have been manufactured, two fully
assembled with the boundary scan completed. One ROD is under test, with VME, DSS and FIFO
paths ok. The module must next be tested with the TTC system, and the S-link output must
be tested. There is a minor modification to the original specification, see http://www.te.rl.ac.uk/esdg/atlas-flt/.
The Xilinx ChipScope signal analyser has already proved very useful in examining
The schematic capture for the module is beginning,
using new Cadence version, but hampered by the loss of some work due to server problems.
Finish data, end Oct/early Nov. The adapter link cards which adapt the TCM to specific
crates must be designed. Three TTCdec cards are available (tested). The new DMIL TTCrx
ASIC will soon be available, with an altered pin-out (121-pin 15mmx15mm BGA) requiring
some mods to the TTCdec card.
Common Merger Module: Norman
The CMM has passed its nominal PDR target date, with
some work remaining on the specification. Other priorities are likely to delay the review
until at least late Nov (see below). Tony offered to help Norman produce the
Backplane Connectors and Cabling: Richard
Sam has put out v0.4 of the backplane spec.
of various review items is as follows:
The backplane spec is almost final, and will be reviewed in late Nov at CERN or in Mainz
by NG, VP, US and RS). This is some 2 months past the target date. (NB. PDR date set for
20th November, after this meeting).
The CMM draft spec is almost ready, and will be reviewed in Dec at RAL (+3 mths) by EE,
SS, US and RS.
The CPM schematics will be reviewed informally in Nov by VP and one other (+2 months).
The JEM spec is in preparation, hopefully final by December, to be reviewed in Mainz by
NG, SH, PH, RS (+2 months).
The PPM should have its PDR in December, pending some problems with ASIC pin-out. The
Preprocessor MCM is due for its FDR in December, but is delayed by the Preprocessor ASIC.
The net result of the delays to these key components is that the 2001 test programme is
likely to be delayed by 2-3 months. The list of milestones should be updated.
Norman added that a Level-1 system may be required in "full-slice" tests at a
CERN test-beam in 2002, from April onwards.
Where are a set of 9U crates for 2001 tests coming
from? LEP crates may remain in use in 2001. ATLAS ROD crates will not be available until
Q3 2001 (Chris Parkman). Old demonstrator crates could be used for some purposes.
Online Software: Norman
The DAQ-1 skeleton is running, largely complete, yet
with key parts, such as buffer and monitoring, missing. Code for the ROD and DSS has been
written, for building RoI fragments and getting them to the buffer manager. Scott is doing
some histogramming code and an event dump, Bill is looking at test vectors, and Reg is
taking up the ROOT work that Tara began. It is seeming difficult to converge in the use of
hardware descriptions common with the HDMC package. The required components for the ROD
tests are not yet in place.
There seems to be a shortage of effort and a slippage in schedule. Lvl1 can expect a
contribution of 1/3 of a person from the Level-2 pool, after the new post is filled.
Effort and productivity need to be reviewed in view of the large amount of work remaining.
ATLAS Week and ROD Workshop: Norman, Ed
Andy Lankford chaired his first major ATLAS meeting in
charge of TDAQ effort. Aggressive plans arre being formulated to build and integrate
Trigger/DAQ prototypes before writing the T/DAQ TDR. There is a data rate crisis, where
the proposed final data rate of 100 Mbyte/s is looking more like >500 Mbyte/s ... some
physics channels may have to be sacrificed. ATLFAST has been ported to ATHENA. LHC is also
looking hard pressed for operation in 2005.
ROD designs have advanced hugely since the last
workshop two years ago. Talks from the ROD workshop are available at: http://dpnc.unige.ch/atlas/rod00/rod00.html
There is another TDAQ week Nov 13th-17th.
Future Meetings: Eric
Next UK meetings:
Dec 1st RAL (TBC)
Jan 23rd RAL (TBC)
Next Joint meeting: Mar 1st-3rd Birmingham