ATLAS-UK Level-1 Calorimeter Trigger Meeting
Tuesday 17th July 2001- Birmingham
Barnett (minutes), Ian Brawn, James Edwards , Eric Eisenhandler (chair), Norman Gee, Tony
Gillman, Bob Hatley, Stephen Hillier, Murrough Landon, Gilles Mahout, David
Mills, Ed Moyse, Richard Staley.
Last Meeting (June 5, 2001)
Generic Test Module........................Ian
for Viraj 10'
Cluster Processor Module.........................Richard
CP/JEP ROD prototype.......................Ian
for Viraj 5'
Common Merger Module.................................Ian
Parallel LVDS transceiver test card........Ian
for Viraj 5'
Timing Control Module & adapter, CPU
Crates and power supplies for slice test.............Bob
JEM and backplane status summary....................Tony
Online software packages and documents..........Murrough
Simulation and test vectors........................Steve 10'
Offline trigger simulation status.....................Ed
LAr and TileCal receiver situation..................Eric
Rack layout developments........................Murrough
RODs, ROD-crate DAQ, S-links, ROSs, and
implications for final ROD
Ian reported that rework on the GTMs required by the
provision of incorrect parts to the assembler has been given up. The new GTMs are,
however, now available, and await JTAG test equipment to become available. (That equipment
is rigged for other tests, scheduled to be completed in about 2 weeks.)
A local company proposing to offer rework services has been
visited by a group from RAL (PPD and ID). The visit was very useful, but questions remain
as to the ease of reworking components placed in the middle of 9U boards.
Eric asked Richard whether a rework test could be arranged,
and Richard later agreed to provide something (for example) with a quad flat pack mounted
to facilitate tests. This after a discussion which highlighted the need to find a
meaningful test, with minimum labour requirements.
Norman pointed out that an outcome of the visit was a further
understanding of the kinds of design rules which need to be followed in order to ensure
successful rework. The company felt that RAL's design rules were for the most part
appropriate, but it would be helpful for the design office to hold direct discussions with
James discussed the status, mentioning that the BC-demuxing
has now been modified to reflect the new "where is zero" labelling conventions
proposed by Steve, with the result that the "chip" simulation now agrees with
The question of the timing difficulties that were encountered
in the design arose, and it emerged that these had been solved by an update in the Xilinx
tools. James is currently checking the timing of the design for the XCV1000 and 1600
Richard mentioned that the Cadence libraries will also need
an upgrade: Panagiotis is attending to that.
Richard presented a summary of the CPM prototype
design, for which the schematics have been completed and now appear on his web. Richard
expressed thanks to James for reading through them in an effort to spot errors,
inconsistencies and omissions.
Richard flagged a CPM design change, which sees the
serialiser configuration store incorporating both the ROC and Hit-sum FPGA configuration
information. In addition, after a discussion with James, he has routed outputs from FPGA
spare pins (16 for each CP, 8 for each serialiser) in an effort to allow their use in
subsequent firmware revisions, should the need arise.
The FPGA-CPLD firmware design status was outlined, with all
items now complete.
A few changes in the module programming model have been
incorporated, with details available on Richard's web page.
Richard gave an overview of the anticipated timescales. He
expects first module tests to commence in Birmingham in November (2001). Layout can start
in the RAL drawing office soon.
On Richard's list are assembly of documentation and provision
of a user guide for the module.
Ian discussed the status, from his and Viraj's perspectives.
He needs tests to be completed as soon as possible so that the production of new modules
can be authorised.
The Birmingham group expressed interest in a ROD/DSS system,
in order to help speed the completion of those tests.
Ian discussed the status of the CMM. In particular, the
question of CMM/CTP interconnection had arisen, with ID proposing to CERN the use of a
standard SCSI-3 type cable/connectors. CERN had proposed an alternate solution, but it is
not clear that the cable impedance of that solution will be appropriate. As the design of
the CMM now awaits this decision, it has been decided to use the SCSI-3 for the purpose of
the CMM prototype.
The CMM design is now ready to proceed to the drawing office,
which has an available slot. The question of whether CMM or CPM should be placed in that
slot arose: the CMM is ready now and will proceed.
Eric reminded [Norman/Ian] that he needs to have a completed
specification for entry into EDMS. This will be provided when changes to the address map,
which are pending, have been completed.
Concerning the choice of connector, it was decided that
Norman and/or Ian should contact Georges Schuler explaining which connector we are using -
and why - in order to have his reaction.
Ian summarised the status on this test card. The design is
ready, but it has not yet been decided how to proceed. The priority given to the card has
to depend on the fact that it is only crucial to the CMM tests, and hence its scheduling
should be consistent with that fact.
In fact there are 3 cards:
- LVDS I/O
- Backplane adapter
- CPM emulater (LVDS to CMOS) so drive CMOS levels into the CMM
The first can likely be done in Birmingham, and the latter
two at RAL (to be confirmed with Viraj).
Bob presented the status of the TCM. The TCM,
Adapter Link Card (ALC) and Display PCBS have been assembled, and appear to have no
serious design errors. The TTC distribution is ok. VME and CANbus functionality have not
The VMM (VME Mount Module) PCB is being manufactured; the
metal work required for processor mounting is ready.
Bob described plans to test the VME functionality of these
modules by using an old 9U backplane with a kludged backplane-to-module connector. In
addition, the CPLD coding has been completed but not yet tested.
The Fujitsu CANbus implementation on this board will be
tested at RAL with the help of, and code prepared by, Dave Mills. In this area some tests
will be required to test the controller's ability to read the VME crate number, etc.
In addition, documentation for the modules needs to be
Concerning the specifications of the TCM, Bob commented that
Paul Hanke had been informed, and had not expressed any reservations thereof [implying
Bob commented on the status of Power Units for the slice
tests. All components have been acquired and the prototype is 80% complete.
Concerning the TTCdec cards, 7 have been made and await
testing. This makes, then, a total of 10 such boards (3 old and 7 new). That is in
addition to the CERN optical test cards of which we have 4 (and which can be used only
with the DSS.) A Test Board for the TTCdecs comprising socket and logic analyser leads is
available. Additionally, we should remember that the new radiation hard TTCrx ASICs will
require a redesign of the TTCdec card, and that this must be done fairly soon.
Tony presented the status of the JEM and Processor
backplane (PRB) work. Sam updated Tony on the status of the PRB, and indicated that the
routing was progressing well, with C. Bohm taking care of the details personally. The
target for completion of the routing is 31 July, and although the work is very time
consuming it is nevertheless hoped to finish on target.
Concerning the bidding procedure, the bids are being examined
and a choice must be made by 4 August, when the bidding procedure closes. It was noted
that the backplanes will be delivered with connectors fitted, but will require manual
removal of the 'extra' pins. (A piece of interesting news is that with the turmoil in the
telecoms industry some components such as connectors are becoming much easier to obtain on
Tony updated us on the milestone status, and on the schedules which are pertinent. (ROD/TCM/VMM/PB;
GTM/CPM/CP-CHIP/CMM) Items in which there is direct UK involvement are shown in blue in his
transparencies. From this it is seen that one might anticipate the beginning of slice
tests around Easter next year: The holding item would appear to be the CPM.
Dave Reported on the status of the Fujitsu CANbus work:
- The ELMB code has been split into 2 pieces, one of which is
- It has become clear that the Fujitsu has different timer
characteristics from ELMB. Dave is working on a solution.
Dave agreed to provide Bob with Fujitsu code to test the TCM.
He will visit RAL, with his testboard along for comparative purposes, to make initial
tests of the Fujitsu on the TCM.
Murrough reported on the status of discussions which
have taken place in an effort to define the "package" structure of our software.
A context diagram and initial package definition are contained within a new draft document
which attempts to define the packaging relevant to the level-1 calorimeter trigger.
Another important document which has emerged is a new
requirements document. Its form and content make it more appropriate than its predecessor.
Both of these documents are the result of a good deal of
internal discussion within the software group.
Murrough discussed the status of some additional draft
documents, and the procedure which might be used to move them to reflect the software
group consensus. It was suggested that the software people should come up with a proposal
to define this procedure.
Steve indicated that he was currently working at high
priority to produce vectors for James' CP-chip tests.
Ed summarised the status of his work, indicating that he had
been mostly fixing problems and fulfilling requests for functionality in his code. He has
been in the process, also, of updating his code to support the evolving Athena, in
particular StoreGate - which has been a major change. No significant new algorithmic
changes (ie: no Jet trigger simulation) have been incorporated of late.
Eric outlined the content of informal discussions with Bill
Cleland, concerning the LAr receivers. These should be available next summer. Bill has
some ideas about what arrangements might be made to build the TileCal receivers. It would
be hoped that some design based on the LAr receivers might be found, but the group he has
in mind can not at this point make a public commitment.
Murrough gave an overview of discussions that he had with Mark Hatch. In particular, there are some
new features in the USA-15 building:
- There are to be 5 cable holes, not 3 as previously planned,
with the central hole reserved for magnet cables.
- The wall adjacent to the middle of our rack real estate really
IS a wall.
Murrough discussed the relative advantages of symmetric and
asymmetric arrangements for the trigger hardware. Asymmetry is preferred by some [eg,
Eric], in particular as it would make the working conditions more acceptable.
Norman stressed that the final latency is as measured,
and that one should optimise all effects that one can predict, in order to maintain
contingency. There is, of course, additional freedom in the choice of the number of crates
per rack: the use of this in latency optimisation could be considered.
Eric commented that it was hard to make decisions on what are
somewhat nebulous criteria: it is not clear at the moment how to arrive at the best
decision. It was suggested that one should stew a little on the latency figure in order to
clarify the ideal choice.
Norman's presentation was divided into two parts.
The first was a discussion of RODs and S-Links. This was a
continuation from earlier presentations (eg: Mainz) in which he addressed the question of
the optimum number of RODS, as related to the number of S-Links each can support.
Norman flagged the availability of an S-Link transition
module which provides up to 4 S-Link LDCs for connection through to the VME J2 and J3.
Either the boards could be externally manufactured or the design brought back to RAL.
There are some technical questions to be followed up, for
example the question of whether the placement of TTC or CAN on J0 would pose constraints
on the physical form factor of the quad-board, but such a module would seem to address our
needs in an ideal way.
In the second part of the talk, Norman began by outlining the
main features of the 'online' and ROS subsystems. He continued by sketching the
architecture and use of CERN Testbeam software. He then outlined the options for test
systems, in particular for our own, and listed the main constraints that impose themselves
on our choice of solution: "ROS-PC" or "ROD Crate/Test beam DAQ".
Given these constraints [and in the absence of some which have been clarified since] he
proposed the adoption of a solution of the latter variety.
Eric mentioned that he still had not received all
contributions for the Mainz minutes, and requested that he should.
Good news from Mainz is that they will soon be joined by a
new member, part of whose responsibility will be to contribute to the software effort.
Tony reminded the group of the upcoming LEB presentations,
and the need to define who should write and present them. There are, it will be recalled,
two twenty minute talks: one on the CP/JP ROD and another on the use of generic hardware
adapted to specific applications by the variations in the firmware.
- October 15-19, 2001: ATLAS Week (CERN)
- November 8-10, 2001: Level-1 Calorimeter Trigger
Joint Meeting (RAL)
- November 12-16, 2001: T/DAQ Week (NIKHEF, Amsterdam)