ClusterAlg.gif (577 bytes) The ATLAS Level-1 Calorimeter Trigger

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ATLAS-UK Level-1 Calorimeter Trigger Meeting

Thursday 19 May 2003 at RAL

Present: Adam Davis, Bruce Barnett, Ian Brawn, Eric Eisenhandler (chair), John Garvey, Norman Gee, Tony Gillman, David Kant, Murrough Landon, Gilles Mahout, Tamsin Moye, Viraj Perera, Weiming Qian, Dave Sankey, Richard Staley, Jürgen Thomas, Peter Watkins, Alan Watson


Click this side                               Click this side
for summaries                                for slides (pdf)
Hardware current and future
CMM 1.0 and 1.1 status..................................Ian
ROD 0.1 hardware, test and firmware status............Bruce
ROD 1.0 specification status..........................Viraj
CPM 1.0 tests and CPM 1.1 status.............Richard/Gilles
BER tester for LVDS..................................Tamsin
Bit and pieces.........................................Adam
New TTC decoder and fanout..........................Weiming
Summary of JEM tests at RAL..........................Norman
Hardware schedule......................................Tony 
Online and offline software
Offline simulation.....................................Alan
JEM simulation.......................................Jürgen
Event dump status.................................Dave Kant
Online software summary (1)...........................Bruce
Online software summary (2)........................Murrough

Recent meeting highlights
TDAQ Steering Group, TileCal, etc......................Eric
Brief status of working groups
Front-end rack, patch panel and cable layout.......Murrough
Latency reduction......................................Tony
Any other business
Date of next UK meeting

Hardware current and future

CMM 1.0 and 1.1 status - Ian Brawn (slides)

Ian reported on the status of the CMM firmware, and hardware. The CMM-JE firmware is built around alorithm blocks designed by Andrea Dahlhoff. Development of the CMM-JE Crate firmware has been completed; it has a latency of 2 BCs + 4 ns. The CMM-JE System firmware does not yet run at 40 MHz. The CMM-CP firmware has some minor changes pending, as a result of subsystem tests. Responsibility for the CMM-Jet-Hit firmware has been transfered to Sam Silverstein.

Re hardware: CMM board 1 (v1.0) has been used in subsytem tests. Data from two JEMs were transfered across the backplane and seen correctly at the CMM. The CMM-CP logic was used to process the data, which it did correctly.

Commissioning of CMM board 2 (v1.1) is in progress. It has been boundary scanned and the VME interface has been tested successfully. The logic currently being tested is that which selects and loads the FPGA firmware on power-up. This is the only logic that was not fully tested on CMM board 1. The tests are almost complete and everything so far indicates that this logic works correctly. Once this is finished the real-time and DAQ data paths will be tested. The aim is to finish these tests in three weeks and then have the 4 remaining bare PCBs for CMM v1.1 sent for assembly.

ROD 0.1 hardware, test and firmware status - Bruce Barnett (slides)

Bruce presented an overview of the firmware, hardware and testing status of the 6U ROD prototype module. He began by noting that the firmware status had changed little since the previous meeting, and that there are three firmware variants (JEM Data, JEM RoI and CMM CpData) with serious problem reports with engineering action pending. In addition to this, he noted that James is still waiting for specification of new firmware, and that there are a few specification issues that require resolution. Bruce suggested that in order to improve the rate of progress and resolve outstanding issues that it would be useful to have a strategy and review meeting with concerned individuals.

Hardware testing awaits delivery of modules, but the LabView testbench, designed by Neil Falconer to satisfy the test-stand needs of ID, is complete. RODS are anticipated to arrive soon. In the Lab 12 integration lab, some software updates were reported, but the major step in the near future should be provision of hardware and software to provide L1A functionality through the DSS.

Progress in CPM and JEM integration has been made in recent visits by Mainz and Birmingham colleagues. Single slices have been passed through the hardware with consistent results in the case of the CPM, and somewhat sporadic ones in the case of JEM. Software work is now required to run the ROD with a single input channel, with hardware within a single T/DAQ partition. The next integration system should strive for this, with as great an integration as possible with the simulation package as well.

ROD 1.0 specification status - Viraj Perera (slides)

Draft 0 is currently being prepared, to be released by the end of this week in advance of a brainstorming session beginning of June. Then version 1 of the specification will be released around the 18th of June for a PDR beginning of July before the QMUL meeting. There is approximately 6 months between PDR and a module being required around January 2004. This is a very tight timescale, and hence the strategy would be to use as much as possible from the 6U prototype design such as the firmware, avoid unnecessary complications such the use of PMC cards (not tested in th 6U ROD), future-proofing the design by making it possible to add things such as compression later on for example by using Xilinx Virtex-II Pro FPGAs with the PowerPC on it, use of modular design techniques to reduce time in DO, etc. The module will be designed by Ian, James and Panagiotis. There will be 18 G-links input, and four S-links output on a separate rear transition module. Of these, all four will be used for DAQ readout and two on RoI modules (one for level-2 and one for DAQ). Processing will use four FPGAs for the S-link outputs and one for RoIs (no compression).

CPM 1.0 tests and CPM 1.1 status - Richard Staley and Gilles Mahout (slides)

Richard: CPM no. 1 had its internal 1.8V Power Module (PM) fail while running test software. A working PM was taken from CPM2 (having faulty CP FPGAs) while awaiting a replacement. Both CPM1 and CPM2 are now up and running again. No other damage has been found with CPM1. The faulty PM will be returned to manufacturer Texas Instruments for examination. It seems unlikely that the faulty PM was being over-stressed, running at about half its rated current output and only running slightly warm.

CPM no. 2 only had four CP chips visible in JTAG testing, but five seem to work and can be configured.

CPM no. 3 was back from assembly , but had problems with the soldering of the small Serialiser FPGAs onto the PCB. The CP FPGAs appear fine, which is in contrast to the experience of CPM2. CPM3 will be returned for replacement of all the Serialisers by new ones. The surface plating of the PCB may be suspect, so is under investigation by RAL.

The re-design of the new CPM is underway for submission to the RAL Drawing Office in July. The changes will be kept to a minimum, the main work will be to re-route the backplane inputs for better signal quality, and to improve the clock distribution. The new layout will accomodate the new TTCdec card, which uses a completely different connector.

Ten more LVDS source cards have been ordered, bringing the total to 20.

Gilles: A Bit Error Rate to 10–13 has been performed on 16 LVDS receivers of the CPM#1 (CPM fully populated). No pseudo-random pattern data were used, just a ramp of data so far. The 1.8 V power converter failed for an unknown reason and has been changed. The board is working correctly after the modification, nothing has been damaged.

A TTC scan has been performed on CPM#2 by sending data between SRL playback memories and the four working CP chips. It appears that five CP chips are working in fact rather than the four expected from JTAG, and TTC scans give similar results as the CPM#1. Unfortunately, the working CP chips are not grouped together.

An attempt to fix the deskew1 clock of the DSS has shown that if the option is there, it does not seem to work correctly. The clock could be chosen, either deskew1, deskew2 or main clock, but it seems to ignore the value of a given timing.

CPM#1 was brought to RAL in order to be integrated with a ROD and a CMM. Stand-alone tests have been repeated and failed. The CP chips do not behave correctly, either in Scanpath or algorithm mode. The main difference between the setup at RAL and the one at Birmingham, is the use of a CPU board inside the VME mount module, instead of a Bit3 system. The F/W Done signal disappears during a run, due to generation of a reset on board. It is not understood why , but this could be another problem due to the use of the VMM and its SBC. It is not possible for the moment to reproduce the problem at Birmingham, as the booting system there is still on disk rather than on the network, and the VMM shows some problems when booting on disk.

Among other tests at RAL, the CPM has locked and received correctly LVDS data from an external DSS. TTC scans have been performed successfully and the result is similar to what has been recorded at Birmingham. DAQ one-slice data have also been sent to a ROD, but of the four inputs of the ROD, only one receives some data. The length of the data are correct and data seems to make sense. If the rate of Level-1 Accepts increases, nothing seems to be received correctly and the length of data is wrong. In addtion to understanding this, a test of sending data to the CMM must be carried out soon.

On the software front, an environment has been created to run the CPM at RAL. The Status panel udates some values and firmware are now loaded from Database.

BER tester for LVDS - Tamsin Moye (slides)

In order to produce a BER tester for LVDS, the serialiser code was modified by introducing an "error_comparator" component. A block of RAM in the serialiser was filled with a known data pattern coming from the DSS. The error_comparator synchronises the data playback from memory with the incoming data from the DSS, and then compares them for errors.

The program now works fully, locking when the data matches, and counting errors if they exist. Numerous problems including errors occuring when VME access was made, have been overcome. The code has been improved to test all four input channels to the serialiser, and a full board of 20 serialisers has been populated and tests run overnight. As a result of such tests, a bit error rate of 2x10–14 has been tested, well beyond the tolerated rate of 10–13.

The current development is to improve the code to generate random data, as is done in the DSS, to test a full range of possible data rather than just a 128 word pattern, repeated over and over, as written in the memory in the serialiser. By using the same seed as in the DSS, and the same technique for generating data (Linear Feedback Shift Register (LFSR)), identical data can be produced and the error_comparator can synchronise this with the incoming data, and check for errors. Relevant code has been received from James, and the error_comparator component within the serialiser is currently being modified to generate this data. Tests can then be re-run to fully measure BER.

Further plans for testing include populating all serialisers on both CPMs in order to test for cross-talk between the boards. Further ahead there are plans to carry the code across into the CP chips and run similar BER tests there.

Norman asked Tamsin to think about whether similar tests could be implmented on the backplane links to the CMM.

Bits and pieces - Adam Davis (slides)

GIO: Two cards have been fully assembled and tested, another six have been made and are awaiting boundary scan.

DSS: New test software developed by Neil is complete. Eight new DSS's have been made, of which six have passed boundary scan and two have problems. The new heatsinks have been made and fitted.

ROD: Individual test software complete, DSS-ROD link software almost complete.

New TTC decoder and fanout - Weiming Qian

The TTC fanout final specification has been finished. Schematic design will begin very soon when the Cadence software license issue is sorted out.

The New TTCdec card specification has been sent out for comments. Final specification will be finished on 30 May.

Summary of JEM tests at RAL - Norman Gee (slides)

Norman summarised the results of recent tests with the JEM (see also the related CMM tests described in Ian's talk, and ROD tests described by Bruce, both in these minutes).

JEMs 0.1 and 0.2 had already communicated over backplane (FIO links) by the end of the previous tests. In the most recent tests, there was a first attempt to run jet and energy code together in JEM 0.2. Teething problems included ordering of nibbles between input and main FPGAs, the convention for clocking data into the main FPGA, and register access in the combined design. There was a second and successful attempt to run a CMM with a JEM, and also with two JEMs. The talk includes screen dumps of collected data. There were also further tests of running with a ROD.

Overall, most of the time went in firmware and software work. To progress faster, a way is needed to modify JEM firmware from RAL during tests. Better preparation for software integration would help – for example, it was complex and time-consuming to get database and system dependencies correct. It would help a great deal to have histogram outputs to look at. On the positive side, the hardware generally started much quicker, and for example LVDS links were up within 12 hours. The improved infrastructure in Lab 12 makes life much easier.

Norman commented that many people worked very hard and long during the tests – but the rate of progress is not yet fast enough to meet our schedule.

Hardware schedule - Tony Gillman (slides)

A first part-populated PPM should become available in September 2003, for final checks on CPMs and JEMs. The remaining tested PPMs for slice tests could be available by end-December. (We should be asking now about test software for the PPMs and PPM firmware for the RODs.)

The 9U ROD programme for slice tests will be lengthy (>12 months for tested modules), so it is essential to get brainstorming on the specification and the PDR underway immediately. (At least two 9U RODs are needed for slice tests; others could be 6U.)

Slice tests will be a programme of continuous evolution – a complex series of interfacing tests with two versions of both CPMs and JEMs – concluding with tests using final-design modules (CPMs and JEMs) in April to June 2004. One month into this final slice-tests phase, module design iterations could start. Final Design Reviews and Production Readiness Reviews could follow at 1-month intervals. (Note that the schedule presented does not yet show beam tests in 2004.)

Staggered production of modules could start in October 2004, running until March 2005. Preprocessor installation and integration with calorimeters still need to be worked out in detail, but will be from May 2005 to July 2006.

Details of the CP and JEP test programmes also need to be worked out. CP and JEP installation and integration with PPr will be complete by mid-2006. Final tests of the full calorimeter trigger system must be completed by October 2006, ready for the cosmic-ray run starting in November 2006 – this is only 42 months away. The first very tight milestone is the start of the extensive module PRR process in only 14 months from now ...

Online and offline software

Offline simulation - Alan Watson (slides)

TrigT1Calo has now been extended to include all algorithms (Ed) and noise in trigger towers (Alan). Integration with the calorimeter towers is still not complete, so HLT TDR studies are being carried out with the Atrig-like trigger tower simulation. Threshold sharpness and trigger rates have been studied using DC1 data, and the results are comparable to, or in some cases better than, the rates calculated using Atrig for the L1 TDR.

Current "trigger menu" proposals from Thomas and Stefan seem to suggest that our 16 em+tau thresholds might not be adequate. However, these proposals do contain a hierachy of inclusive thresholds and several prescaled selections. Alan will discuss these further to try to identify what is really required, and hence whether additional thresholds will be needed.

JEM simulation - Jürgen Thomas (slides)

The basic simulation code for the JEM running within the simulation framework has been provided by Sam Silverstein's students A. Oscarsson and D. Oijerholm-Strom in April. This code follows the hardware structure of JEM 0. The algorithm itself is based on the C++ simulation of the jet algorithm by Sam. It provides the results in the hardware output format.

This code has been modified and put into CMT as package jemSim by Steve Hillier. Playback memories have been implemented, and the input reader developed for the JEM hardware tests has been interfaced. The energy summation tree has been adapted to the firmware (as in old simulation), but slight deviations in SumEx and SumEy need to be examined that occured when running with physics (tt) test vectors. A first integration into the dbSim environment has been done by Steve.

Further work will focus on interfacing the database for all settings, checking the jet algorithm and providing readout data files needed for the next JEM hardware tests at RAL.

Event dump status - David Kant (slides)

The current release of the ATLAS online event dump program is a Java utility written by M.Mineev. The basic idea behind this program is to provide general methods for rendering event data fragments. The code is flexible enough to allow groups (e.g L1Calo Trigger) to provide more specialised methods to enhance the description of their data.

The purpose of this project is to investigate the event dump component of the online software with the aim of customising it to display L1 Calorimeter event fragments in a more comprehensible way. This component is called "L1CaloED" and a web page describing the present status of the project is available at:

A list of requirements (version 0.2) is also available. Gilles suggested trying the dump with the CPM.

Online software summary (1) - Bruce Barnett (slides)

Bruce offered some comments on status and direction in computing, software and testing. He outlined the progress made at RAL in deploying RH7.3.2 Linux. All machines are now running that OS, and the transition of the L1Calo software (in particular in (ML) packages close to the online – now at version 19) is complete. Clones of the RAL system will soon be deployed at Birmingham and Mainz. The migration strategy in future depends on the CERN strategy, to be discussed in a CLUG meeting and within the forum of the certification committee at CERN in the near future.

Concerning ROS, driver components have been compiled at RAL, and a recent (00-04-00) version of the ROS packages installed. It will very soon be time to quicken the progress in this direction – in particular in the purchase of new hardware (HOLA, FILAR and PCI-X PC).

In general, much code is maturing within L1Calo, but the time is rapidly approaching when solidification of that code – using the full power of all L1Calo packages – will be demanded. There is much to do. It is Bruce's opinion that the time has come for a strategy review to itemize the list of things to do and determine the critical path. This will be mandatory for a successful slice-test programme.

Online software summary (2) - Murrough Landon (slides)

Murrough gave a brief summary of the recent software progress, the details of which were mostly covered in other talks.

The main activities have been integrating modules into the developing slice tests and the migration of our software to new versions of the OS, Qt and the Online software. The move to the latest Qt involved some porting work in HDMC.

Other developments which are mainly still in progress are moves towards support for multistep runs both for calibrations and for loading sequences of test vector files. These are implemented but still need to be tested on a real system.

There are many major items still on the "to do" list including use of the ROS and monitoring framework together with the use of the DSS to generate TTC signals.

It was noted in the discussion that software for the forthcoming PPM will soon be a critical item.

Recent meeting highlights

TDAQ Steering Group, TileCal, etc. - Eric Eisenhandler (slides)

At the May meeting of the TDAQ Steering Group, it was reported that the HLT/DAQ TDR is now going fairly well. A second draft was released on 7 May, and some updated chapters have appeared since then. The ROB-on-ROD option, which had already been turned down, had then been re-proposed by some people. Feedback had been sought from the detectors, and they were unanimously against it, essentially because it mixes ROBs that are DAQ responsibility with RODs that are detector responsibilities – this muddies a very clean interface, in order to save some money. The TDSG has now unanimously rejected the proposal and the proposers have said they will accept that. Other items were discussed – see the minutes when they appear.

While at CERN, Eric had talked to Rupert Leitner and Richard Teuscher of the TileCal group. Two PRRs for long cables (the first before tendering, the second before purchase) are planned, thought it is the same specifcation as LAr cables. Can we possibly order our short cables at the same time?

It is suggested to look at TileCal pulses with prototype cables (they have some already) and a prototype LAr receiver in the test beam – contacts are Richard Teuscher, Tomas Davidek, and Bob Stanek; running periods are 12–18 June, 3–9 July, 23–30 July, and 20–27 August.

Information from Bill Cleland on putting unipolar TileCal pulses into receivers via transformers, which produces a bipolar pulse, is that the negative undershoot has a time constant of ~10 microsec. Equal areas mean that a pulse of e.g. 200 GeV has an undershoot with a peak amplitude of ~1 GeV. To evaluate whether that is ok we need information on pulse rates and amplitudes. A plot was shown that Richard Teuscher had sent and it seems to be ok; the occupancy is low and the pulses quite small.

Eric also had a discussion with Beniamino di Girolamo concerning his draft document on commissioning. Our requirement to read out both calorimeter and trigger RODs at the same time, in order to integrate the Preprocessor, is now recognised and a solution will be provided.

Brief status of working groups

Front-end rack, patch panel and cable layout - Murrough Landon (slides)

A working group to discuss our front end layout was set up by Eric and consists of Paul, John, Murrough and Steve. The group has had one meeting whose minutes may be found on the group's working web page: One query that has appeared is the length of G-link cables to RODs that are feasible.

Latency reduction - Tony Gillman (slides)

The aim is to assess current the overall latency budget, by comparing individual sub-systems' envelopes to the official document which was based on the TDR architecture. Then look for the most promising areas for potential savings. There is some urgency if we want to influence new module designs. The working group has at least one representative per sub-system: Eric, Tony, Paul, Murrough, Gilles, Uli, and Sam, and will meet via weekly phone conferences, starting May 21st.

Organisation - Eric Eisenhandler

Eric is consulting people, but it is going quite slowly.

Any other business


Friday, 13th June at Birmingham.

Eric Eisenhandler, 4 June 2003

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