Present: Bruce Barnett, Ian Brawn, Eric Eisenhandler (chair), Florian Föhlisch, John Garvey, Norman Gee, Tony Gillman, Steve Hillier, Murrough Landon, Gilles Mahout, Adrian Mirea, Tamsin Moye, Viraj Perera, Weiming Qian, Dave Sankey, Richard Staley, Dimitrios Typaldos, Jürgen Thomas, Peter Watkins, Alan Watson
Click this side Click this side for summaries for slides (pdf) Subsystem tests Overview of subsystem tests...........................Bruce Cluster Processor testing............................Gilles Energy-sum and jet testing...........................Jürgen Processor hardware and firmware CPM 1.5 status......................................Richard CMM status..............................................Ian 9U ROD specification status..........................Norman 9U ROD prototype and firmware.........................Viraj ROS status............................................Bruce CANbus and DCS working group...........................Dave TTC.................................................Weiming Firmware working group................................Steve Trigger interfaces TileCal patch panels...................................Tony Highlights of TDAQ week at CERN... ..Norman/Murrough/Gilles/Jürgen/Dave/Adrian/Dimitrios Online and offline software Offline simulation.....................................Alan Online software summary............................Murrough Schedule Slice test planning...................................Bruce Testbeam planning and discussion of who is... ...available when......Norman Hardware schedule and milestones.......................Tony Any other business – Long-term attachment – Papers for conferences Date of next UK meeting
Summary not yet available.
Two new CPMs, version 1.5, respectively called CPM6 and CPM7, are now under test at Birmingham. The design is very close to the old PCB, the front panel has two new connectors, one for JTAG and one for a couple of testpoints. An optical output for the readout is added on top of the electrical one and extra clocks are provided to the CP chips.
After checking that VME access and FPGA downloading were behaving correctly, a timing scan of real-time data for on-board signals was performed. The overall timing window is around 3ns, slightly wider than on the old board. Clock tracks have been carefully kept to the same length, and when we repeat the scan by using the self calibration, where each individual pins could been assigned a different phase, two peaks appear in the width of the error peak. It corresponds to the time difference between the groups of EM and hadronic serialisers, due to the difference of track lengths. Looking at each individual pin, the timing window is around 4ns, 500ps more than the old CPM.
The timing scan of the backplane data shows no improvement, the width of the peak error still being wide due to the spread of track lengths between serialisers. Careful investigation of the routing of those tracks shows that delay up to 2 ns could be observed between two serialisers talking to the same CP chip. One solution to reduce the spread will be to drive some backplane pin I/Os with the additional clock of the CP chip at a different phase. Firmware for the CP chip has been written in which a register can be set in order to select the clock driving the backplane I/Os. This need to be tested but it is hoped to save at least 1ns.
Some pins do not seem to work correctly, as if they were not correctly connected. After re-routing these faulty pins to some testpoints available on the board, they appear to behave correctly. So it is still not understood why this is happening. Two CP chips have the same problem, and the faulty pins are at the same location, which makes them suspicious.
Concerning the readout, the board has been very successfully integrated at RAL, and has been running without losing any lock. The deterministic jitter has disappeared thanks to the new TTCdec card. Optical output has also been tested successfully. Finally, CPM7 is also working correctly, except for the backplane I/O where similar problems to CPM6 are also observed.
Another integration test is scheduled at RAL, to test the new serialiser firmware written to accommodate the PPM handling of the parity. Those tests will also be dedicated to looking at the CTP output.
The JEM 0.2 is now completely broken, with two FPGAs not being configurable. It will not be reworked as JEM 1 completion is imminent. In order to be ready for the test beam, JEM 1 needs to be integrated at RAL in early June. JEM 0.1 is alive at RAL and can be used to source the CMM/Sum tests. In the last CMM test days, the Energy-sum mode was tested with the readout. Most issues are now settled, the main remaining issue is the CTP bits which do not match the simulation. This will be dealt with soon. A test of the JEM 0.1 RoI readout was also performed, remotely sourcing 16 LVDS channels. For a constant pattern, where readout offsets can be arbitrary, the readout data matches the simulation. For a counting pattern, the readout offset could not be found. But as JEM 1 will arrive soon with new firmware, this issue will again be dealt with only on the new module.
The first two fully assembled CPMs with new PCB layout have just arrived from DDi, with no serious assembly problems. These both pass the JTAG test.
VME-- access, control functions, FPGA configuration and TTCrx I2C access are all working. However some CP chips are not reading any data on some inputs. This is still under investigation as early checks show that signals are present on the device pins.
Backplane signal quality is much improved, but there are still timing issues:
In summary, the company (DDi) chosen to make and assemble the latest CPMs has done a good job. There are still some timing issues with the CPM, but these should be resolved once the extra clock is added to the CP chip design. In parallel with this work, the layout will be examined for improvements.
Ian presented a status report on the CMM. Since the last UK meeting he has re-designed VME interface to the CMM-Energy firmware; inserted deadtime between readout events for the benefit of the 6U ROD; corrected the bunch-number sent with readout data; corrected the cable disable mask in CMM-Energy firmware; debugged the I2C interface (see below); and modified the I2C CSR to meet the new CMM and CPM standard agreed with Richard Staley.
Regarding the I2C interface, Ian and Norman debugged this and identified three faults: due to a schematic error. A pullup resistor was missing from all CMMs, disabling a control signal; the I2C control firmware suffered an intermittent fault due to timing glitches; and one of the three CMMs so far tested had no clock to the I2C controller due to a bad BGA joint. These faults can be fixed by: adding the necessary resistor; modifying firmware to protect against timing glitches; using a spare clock input to the I2C controller. Three CMMs have had these fixes applied and now have working I2C interfaces. The remaining two have yet to be modified or tested.
The CMM also needs the following work: the new I2C CSR needs to be tested; the new scheme of substituting parity bits in the readout data with parity error flags needs to be implemented; the format of the data to the CTP needs to be documented; and TTC broadcast commands need to be implemented, for which Ian is awaiting a specification. Ian said this comprised all the pending work that had been documented. He asked anyone who was expecting work which he hadn't covered to submit a request in writing, please, so that a record is created.
Summary not yet available.
Placement of components is almost complete now, it will be a couple of days before moving on to the next stage. This has taken longer than planned and it's a very 'busy' module now.
The S-Link rear transition module design is also almost complete, with one issue to resolve regarding placing the test connectors. This will be sorted out with Bruce soon
The FPGA firmware design is also progressing in the absence of James, who should be back at RAL on the 4th of May. Meanwhile Ian is partitioning the Input FPGA so that Weiming and the others can work on various firmware variants starting with the 'neutral' version.
Summary not yet available.
Summary not yet available.
The jitter measurement result of the LAr FEB group is summarised; it agrees with the TTCdec clock jitter measurement done at RAL. The main jitter source is identified to be the TTCvx module. The TTCex module is much better than TTCvx in terms of jitter performance. QPLL will improve the clock jitter of TTCrx, but not dramatically.
L1Calo G-link readout has a less stringent jitter requirement than FEB. Soak tests with the G-link readout path are needed to evaluate the performace of the Mark3 TTCdec as G-link reference clock.
There hasn't been a recent official meeting of the group, but most attended a demonstration of Synchronicity given on 18th March at RAL by Richard Lawrence and Paul Hardy of the Microelectronics Support Centre. This consisted of a quick tour of the features of Synchronicity, and a brief example of usage. The software features essentially everything that could be expected of a good archiving system, and has one stand-out feature for use by the RAL ID group in that it has an integrated user interface for Mentor HDL Designer, and some other design tools. However, one problem apparent at the demonstration was the rather slow speed of file transfers to and from the archive. Another problem to investigate is how well the archive deals with 'side files' – extra files needed to actually do the FPGA synthesis. These may have to be archived 'by hand', as will data relating to VHDL generators that are not fully interfaced to Synchroniciy. In other respects, Synchronicity has all the features we need for firmware archiving at all Level-1 locations, and is quite cheap.
The current status at RAL is that the archive vault is still being set up, and the ID group should be able to start using it soon. They will however be acting as 'guinea pigs' for the system, which is probably not conducive to a speedy start-up.
One of the patch panels has gone to CERN to be tested by TileCal people. However, they have not started to do this yet.
We began with Norman summarising discussions during the recent TDAQ week, followed by additions from the other participants. The full agenda including all talks is at http://agenda.cern.ch/fullAgenda.php?ida=a04295. Norman's summary is as follows:
Following discussions with the LAr group, the LAr tower simulation has been re-written. The new version needs some refinements (calibrations, addition of FCAL) but is otherwise working correctly. Prototype trigger code is able to read both LAr and Tile towers, and simulate FIR-based BCID, pedestal subtraction and calibration. The first release will produced unchanged TriggerTower objects, but these will later be redesigned to accommodate multiple samples.
Since the talk was given, the Atlfast error which was delaying development has been worked-around by Peter Sherwood, and so a first release may occur in 8.2.0.
Some recent software developments were briefly summarised, among them the move to recent ATLAS software releases and use of the ROS. Work on PPM software and updates for JEM1 are ongoing.
It was suggested that we might start using the conditions database, eg to store and retrieve calibrations. Murrough had some discussions about this with Luis Pedro during the recent TDAQ week. Using the conditions database in our software would make the data stored available to ATHENA but would require us to run a MySQL server in standalone test setups.
Also at TDAQ week there were useful discussions on how we proceed with event monitoring and also on some issues of migrating to use the ROD crate DAQ run controller which we are being "encouraged" to do.
The Pre-PRR schedule has been updated to reflect the further slippages in some areas. The full Slice Tests cannot proceed until the first PPM is
Summary not yet available.
Tony presented a series of three Gantt charts, very similar to those shown at the recent Heidelberg Collaboration Meeting, showing the schedules of the following phases of the programme, leading up to final commissioning of the trigger in 2006:
i) FDR/PRR phase
ii) Module production phase
iii) Installation/Commissioning phase
He then showed the most recent table of Milestones, from November 2003, and a draft of the radically modified version he had prepared in response to Miikka Kotamaki's suggestion for re-baselining. The side-effect of the Combined Test-Beam run in September will be to drastically slow down the Slice Test work, so Tony questioned when and where these systematic tests would take place. He suggested that the majority of the work would inevitably be delayed until after the Test-Beam running, i.e. October 2004, unless the Test-Beam itself could be considered "Slice-like", which he thought implausible.
Long-term attachment: We need to start collecting information on who might be willing to be resident at CERN when, and start correlating that with our requirements for installation and commissioning. This is supposed to be done by the time of the next Joint Meeting.
Papers for conferences: Gilles mentioned the two conferences we usually submit papers to. LECC deadline is in a few days, but the conference is in USA and conflicts with testbeam. IEEE NSS might be better since it is in Rome and is later; we have to do something soon since the deadline is mid-May. It was felt that testbeam results would be more likely to gain favour than slice test measurements.
It was felt that we need another meeting before the next Joint Meeting in early July in Stockholm. One possibility is 4 June – Eric will check if that is ok with people not present. NOTE added later: 2 June seems to be a better choice.
Eric Eisenhandler, 30 April 2004