Architecture

Specifications and Information

• L1Calo Module Specifications
• L1Calo Components: ASICs, Backplanes, FPGAs, and MCM
• External Module and Component Specifications: LTP, TTC, Crates, Receivers
• Trigger Numerology: Modules and Interconnects
• Label Formats for Hardware
• Module Keying for CP and JEP Crates
• Analogue Input Cabling Information – EDMS and Input Data
• Technical Information Notes

• Software: Mirrors at:  QMUL   CERN
• Computing information at RAL
• Firmware Working Group
• Miscellaneous Information

• RAL (ESDG) Module Page
• KIP (Heidelberg) Module Page and Designs-in-work Page
• Mainz Module Page

General Documents on the Trigger System

• Algorithms (pdf) (comments to E. Eisenhandler)
• User Requirements Document, version 1.1 - (pdf) or (other formats) (comments to E. Eisenhandler)
• Technical Design Report (TDR) and Updates

Testing

• ATLAS Combined Test Beam 2004

Demonstrator Programmes

• Complete Slice through Level-1 Trigger (1997)
• Complete Slice BINHEX picture (1997)
• Phase 2 Data Transfer demonstrator (1996)
• Bunch Crossing Identification Demonstrator (1995)

This page was last updated on 13 February, 2009
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