Phase 2 Demonstrator
This second generation bit-parallel trigger demonstrator will be used to study data communication aspects of the final level 1 trigger system.
Documents describing the major components of this system include the following. Except where specified, the format is usually PostScript.
Description of Modules
Designed and built by the University of Heidelberg (IHEP)
Timing Control Module
Cluster Processing Module
Crate system, incorporating a special high speed backplane
This page was last updated on
16 December, 2013