Minutes of Hardware Progress Meeting - 13 March 2001
Present: Bruce Barnett, Ian Brawn, Norman Gee, Bob Hatley, Viraj Perera, Richard Staley
Of two modules handled by the rework company STI, the one whose JTAG works is being
kept for tests and the other has been sent for further rework. STI have been asked to
inspect the board and report after each rework stage.
2. CP FPGA
Ian is serialising the existing test vectors, but would like more. He will liaise with Alan.
3. CPM prototype specification status
Richard has received the CAN controller sheet from Viraj. This will need changes for inclusion in the CPM.
Richard is now working on the FPGA containing TTC I/F, CAN control. and Flash memory configuration control. He has not yet started the ROC. The target date for review of schematics is still end March 2001. Richard will issue a bill of materials so that a check can be made for components with a long lead time. There has been a problem obtaining the required flash memories which can be programmed off the board. Viraj will remind Bob Thomson.
Richard has proposed a new TTC VME interface, requiring two registers rather than the much larger number previously used. The TTC spec claims an I2C bit rate of only 100 kHz, making transactions with the TTC very slow. He will confirm this with Phillippe Farthouat.
Viraj pointed out that the TTC control code could be tested in the ROD hardware. Viraj and Richard will discuss what would be needed to do this. It would have to take place after the RoIB Tests (i.e. after Easter).
Azmat has corrected pulse register problems identified in tests. Viraj asks for an audit of the number required for the slice tests.
5. ROD prototype
Bruce has set up data streams in the DSS such that the S-Link output buffers do not quite fill up. The intention is to check the data, then look at failure modes. The Busy output is not yet working properly.
This is now in the RAL Drawing Office. The main PCB placement is done and the schematics have been compiled. A bill of materials exists. Bob said that front panel dimensions are still required. The Drawing Office is also working on the sub-PCB for the display and on the Adapter Link Card for the Cluster crates.
He has not started work on the CPU adapter card.
6. CMM status
Ian and Norman briefly discussed the new requirement for a JET-ET RoI. To save memory resources on the CMM, a new format is a better idea than extending an existing one, as the amount of data needed is very small.
Ian has been looking at implementation of both the Crate and System level summing in a single FPGA. The proposed clocking structure is a barrier to this, but may be unnecessarily complicated. This will be discussed.
Norman and Ian had checked the backplane space and found some missing and miss-labelled pins - Sam has provided a new version, and we need confirmation that this is the production version. It has 27 rather than 28 pairs between CMMs (25 are needed, others are spares).
Bob will restart collecting power supply requirements.
9. CAN developments
David Mills has problems with the CAN development kits. Viraj will contact him to arrange a time when they could meet with the hardware.
Bob has produced a list of the required Zpack parts. Some have been ordered, but others have a long delivery time and big MOQ. None of the three suppliers contacted has yet yielded a solution.
We need to place the bulk order.
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16 December, 2013