Double Sided ABCD2T Module with Ceramic Hybrids

Preliminary Results

(for the impatient)


Bonding: 30 channels ((315-327) and (1081-1097)) have deliberately been left unbonded to give a point of reference.  There are also a further 11 channels where bonding failed between the chips and fanin, notably a cluster of 7 channels of the last chip on the module.

Voltage settings: Vcc 3.51 volts on support card, Vdd 4.07 volts on support card; Vbias 100V, current <4microA.  Floating linear bench supplies are used; there is a single connection between DG and VME ground to keep the LVDS signals within acceptable common mode limits.  The module is mounted in a "QMW" box, which is connected to GND on the patch card which routes signals between the support card and the module pigtail.  The support card has been modified to connect AG and DG together immediately adjacent to the module connector: this was found to be critical during early testing, when only one side of the module was bonded.

Chip settings: Bias current 267microA, shaper current 30microA.  (These values have not yet been optimised.)  All data shown here was taken with the edge detect circuitry enabled, using 01x data compression.  For the delay register, two values have been used: 50 bits for qinj values below 2.5fC and 55 bits for 2.5fC and above.  It is clear that different values must be used for threshold scans of 1.5 and 3.5fC, but this simple approach with two values is far from ideal.  More work must be done in this area.

Trimming: the module has now been trimmed such that vt50 from a threshold scan with 1.5fC charge was closest to 135mV.  A total of 14 channels cannot be trimmed using this simple algorithm; in other words, for 14 channels there are not values of the trimdac setting which give vt50 points to either side of the target value of 135mV.


The threshold scan data has been reprocessed 28.10.99 to include correct propagation of  fit errors: note the much smaller error bars!!

Threshold Scan, 1.5fC, chips 0-5:, summary.txt, fitdata.txt
Threshold Scan, 1.5fC, chips 6-11:, summary.txt, fitdata.txt

Threshold Scan, 2fC, chips 0-5:, summary.txt, fitdata.txt
Threshold Scan, 2fC, chips 6-11:, summary.txt, fitdata.txt

Quick evaluation of gain and noise by linear interpolation of the above scans:

chips 0-5:, summary.txt, fitdata.txt
chips 6-11:, summary.txt, fitdata.txt
Response curves (sorry, no fits yet) for charges from 1fC through 4.5fC:
chips 0-5:
chips 6-11:
Noise Occupancy: I have fitted the error function to the occupancy data and measure approximately 12.5mV noise.  For 60 mV/fC gain, this equates to 1300 electrons. With a single double sided module as occupancy approaches zero, my event rate is 56.5kHz, so these scans don't take too long.  (I wonder how much faster it can go....)

New plots, 04.11.99

  • Response curves, chips 0-5, module trimmed for uniformity at 1.5fC (as above)
  • Response curves, chips 0-5, module trimmed for uniformity of offset
  • Noise Occupancy scan, chips 0-5 and 6-11, module trimmed for offset uniformity


    Preliminary Conclusions:

  • circa 60mV/fC gain at 30 microA shaper
  • circa 1400 electrons noise for 12 cm strip length measured by threshold scna method, 1300 electrons measured by noise occupancy method
  • There is oscillation (or pickup - t.b.c.) at low thresholds, in the original configuration this cut off sharply at 95 mV threshold (0.85fC)
  • Strapping GND from the bottom hybrid to the patch card inside the QMW box lowers the onset of oscillation to 85mV threshold (0.65fC)
  • Variation of shaper current has no effect upon the upper limit of oscillation when expressed in fC.
  • Noise occupancy ~ 3.5 x 10^-4 at 105 mV (1fC)
  • The module works!!

  • Comments / questions / suggestions: please contact Peter W Phillips
    Last updated 04.11.99