RLT2

12 ABCD2T chips (second batch) on thin film hybrid

* Hybrid * Hybrid Results * Comparison with Chip Test Results * Module * Module Results *

Hybrid Tests

Trimming was performed to optimize threshold uniformity at 2fC.  The optimum target value was found to be 200mV at which a total of 100 channels cannot be trimmed correctly - although this is largely weighted by the performance of chip 5.  If one were to trim for threshold uniformity within each chip, the total number of untrimmed channels could be reduced to 40.  For the time being the setting of the strobe delay register has been optimised only at 2fC.

Shaper current is 30microA and bias current is 267 microA;  Vcc is 3.50V and Vdd is 4.00V as measured on the support card.


Hybrid Results

Trim: 2fC = 200mV
 
HYBRID RESULTS in EDGE MODE/01X
Chips M0-E5
 
 
Chips M8-E13
 
 
Threshold scan 1fC
.ps (~1.8MB)
.fit
.sum
.ps (~1.8MB)
.fit
.sum
Threshold scan 2fC
.ps (~1.8MB)
.fit
.sum
.ps (~1.8MB)
.fit
.sum
Threshold scan 3fC
.ps (~1.8MB)
.fit
.sum
.ps (~1.8MB)
.fit
.sum
Threshold scan 4fC
.ps(~1.8MB)
.fit
.sum
.ps (~1.8MB)
.fit
.sum
Response Curve
.ps (271kB)
.rcdat
 
.ps (271kB)
.rcdat
 

Comparison with Chip Test Data:

 
Position on
Hybrid
Position on Wafer id 3
nDead
(wafer test)
noTrim
(wafer test)
Gain
(wafer test)
Gain @2fC
(on hybrid)
Noise
(on hybrid)
Offset by
Response Curve
Offset by Noise Occupancy
nDead
(trim= 0)
noTrim (2fC=200mV)
0
3,13
0
2
60.1
55.3
600
80
110
0
3
1
3,14
1
4
59.4
54.7
600
83
113
1
4
2
3,15
0
3
60.3
54.2
600
85
117
0
3
3
3,16
1
5
60.4
54.8
600
81
111
0
7
4
4,7
0
5
65.3
54.2
700
82
116
0
3
5
4,10
0
14
68.5
70.7
600
40
46
0
17
6
4,11
0
10
59.7
56.9
600
78
118
0
11
7
4,12
0
8
60.0
53.8
600
83
112
0
11
8
4,13
0
9
58.6
52.3
600
88
116
0
11
9
4,15
1
6
61.6
54.8
600
82
108
1
6
10
4,16
0
5
59.6
53.8
600
85
114
0
5
11
5,5
0
15
56.8
49.0
600
96
121
0
19
 
x,y
 
 
mV/fC
mV/fC
ENC
mV
mV
 
 
 

Module Tests

The module is not sufficiently stable to be retrimmed, hence the old trim file is still in use: 200mV = 2fC.  Shaper current is 30microA and bias current is 267 microA.   The module operates in a standard QMW box, linked to module AG by the patch card.

Low Voltage

Vcc and Vdd are as tabulated below.  All measurements have been made with respect to the potential of the metal QMW module box.
 
 
Power
Supply 
Support
Card Input
Top Hybrid Input
Top Hybrid Output
Bottom Hybrid Input
Bottom Hybrid Output
Vcc
3.627
3.618
3.560
3.533
3.525
3.521
AG
-0.028
-0.019
0.022
0.035
0.048
0.051
Vcc-AG
3.655
3.637
3.538
3.498
3.477
3.470
Vdd
4.120
4.110
4.071
4.047
4.029
4.020
DG
-0.019
-0.003
0.021
0.036
0.050
0.054
Vdd-DG
4.139
4.113
4.050
4.011
3.979
3.966
 
V
V
V
V
V
V

High Voltage

Here is the IV characteristic of the module, measured at 22 Celcius, 30% RH.
 
V
I
25
180
50
650
75
1030
100
1380
125
1750
150
2100
V
nA
 


Module Results

Preliminary!!!
  • List of Bad Channels. A total of 107 channels have been masked, including seven which have been added manually.  In addition to this chip 5, which has abnormally high gain, has been masked from the following plots
  • Noise Occupancy, 100V detector bias, Level mode, both links, scan up and down
  • Noise Occupancy, 100V detector bias, Edge mode, both links, scan up and down
  • Noise by Charge Injection, 100V detector bias, Level mode, link0 and link1
  • In level mode the module is stable down to150 mV threshold when scanning downwards and above 157.5 mV threshold when scanning upwards.  In edge mode the module is stable down to 157.5 mV threshold and above 195 mV threshold when scanning upwards.  So, this module exhibits marked hysteresis in EDGE mode only.  Given the present trimming, 150mV threshold represents something of order 1fC.

    By charge injection method this module returns different noise figures for the two sides.  Link0 returns 1500 ENC and link1 returns 1700 ENC.  The reasons for this discrepancy are not yet understood.


    Modified 18.01.00
    Comments / questions / suggestions: please contact Peter W Phillips